1. Field of the Invention
The present invention relates generally to processing substrates, and more particularly to methods and apparatuses for removing material from a substrate.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features in semiconductor substrates is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on semiconductor manufacturing capabilities. Reliable formation of interconnects is important to the processing of VLSI and ULSI successes and to the continued effort to increase circuit density and quality of individual substrates.
In general, multilevel interconnects are formed using sequential material deposition and material removal techniques on a substrate surface to form features therein. As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization prior to further processing. Planarization or “polishing” is a process in which material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing excess deposited material, removing undesired surface topography, and surface defects, such as: surface roughness, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials in order to provide an even surface for subsequent photolithography and other semiconductor manufacturing processes.
It is extremely difficult to planarize a metal surface (e.g., copper surface) by electrochemical mechanical polishing (ECMP), which planarizes a layer, by electrical and chemical activity as well as mechanical activity, of a damascene inlay with a high degree of surface planarity. A damascene inlay formation process may include etching feature definitions in an interlayer dielectric, such as a silicon oxide layer, depositing a barrier layer in the feature definitions and on a surface of the substrate, and depositing a thick layer of conductive material, such as copper, on the barrier layer and substrate surface. The copper material is electrochemically and mechanically polished to expose the barrier layer and the copper filled feature definitions or “plugs.” However, electrochemical mechanical polishing of the copper material to remove excess copper material above the substrate surface often results in non-planar topographical defects, such as dishing and erosion, that may affect subsequent processing of the substrate.
Dishing occurs when a portion of the surface of the inlaid metal of the interconnection, formed in the feature definitions in the interlayer dielectric is excessively polished, resulting in one or more concave depressions, which may be referred to as concavities or recesses. As shown in FIG. 1A, a damascene inlay of conductive lines 21 and 22 are formed by depositing a metal, such as copper or tungsten or a tungsten alloy, in a damascene opening formed in an interlayer dielectric 20, for example, silicon dioxide. While not shown, a barrier layer of a suitable material such as titanium and/or titanium nitride may be deposited between the interlayer dielectric 20 and the inlaid metal 22A. Subsequent to planarization, a portion of the inlaid metal 22A may be depressed by an amount D, referred to as the amount of dishing.
Therefore, there is a need for methods and an apparatus for removing conductive material, such as excess copper material, from a substrate that minimizes the formation of non-planar topographical defects to the substrate during planarization.